1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device which effectively removes copper oxide layers on copper conductive lines.
2. Description of Related Art
It is generally known in the art to form a connecting portion as an electric connection between devices of a semiconductor apparatus by adapting a copper conductive line. This technology, however, has numerous drawbacks. A step from a surrounding portion of the connection is often enlarged; step coverage is lowered; and a short between the conductive lines is often caused which leads to low yield rates, since, after plug is formed in a contact hole or via hole of a second insulating layer, conductive line is formed on the plug.
In an attempt to resolve these problems, a Dual Damascene structure was developed that is formed by simultaneously patterning the plug and the conductive line. A copper conductive line adapted to the Damascene structure is advantageous from a point of resistance and reliability comparing with aluminum or aluminum alloy conductive line. The Dual Damascene process for forming the copper conductive line is performed as follows. A second insulating layer is formed on a lower conductive line, a certain portion of the second insulating layer is removed to form a via hole and a trench. A metal barrier is formed thinner on the via hole and the trench to get in contact with the lower conductive line. A copper layer is formed to completely fill the via hole and the trench. The copper layer is formed with a planarizing process and a cleaning process. A capping layer is formed to cover the exposed copper conductive line.
A method of forming a connecting portion and a conductive line of the semiconductor device according to the prior art will be now described with reference to FIGS. 1a to 1d. 
A first insulating layer 102 is deposited on a semiconductor substrate 101 by a chemical vapor deposition (CVD) process. The semiconductor substrate 101 may be a semiconductor substrate with an impurity region (not shown), or a lower conductive line. A lower metal layer is then formed on the first insulating layer 102 by a sputtering method, etc. The lower metal layer is selectively patterned to form a first conductive line 103 using a series of photolithography and etching. Then, a second insulating layer 104 (such as an oxide layer, etc.) is deposited on the first insulating layer 102 and the first conductive line 103, as shown in FIG. 1a. A certain portion of the second insulating layer 104 is then etched and removed to form a via hole 105 and a trench 106 exposing the first conductive line 103. Through subsequent process, a second conductive line is formed in the trench 106 and a plug for connecting the first and second conductive lines is formed in the via hole 105.
A metal barrier 107, as sown in FIG. 1b, is formed on the second insulating layer 104 by a physical vapor deposition (PVD) process. A conductive layer 108 is then formed on the metal barrier 107 to sufficiently fill the via hole and the trench, as shown in FIG. 1c by CVD processing or a sputtering process. The conductive layer 108 may be composed of Al or Cu, etc. When the conductive layer is composed of Cu, a Cu seed layer (not shown) for forming a Cu bulk layer is formed on the barrier layer 107 by the PVD process, and the conductive layer (i.e., the Cu bulk layer 108) is formed in a thickness sufficient to fill the via hole 105 and the trench 106 by an electroplating process using the Cu seed layer. The Cu bulk layer 108 is then planarized to expose the surface of the second insulating layer 104, which forms a second conductive line 108a, an upper conductive line that is electrically connected with the first conductive line, and a plug 108b, a connecting portion between the first and second conductive lines, without a separate patterning process.
In the conventional method of forming the conductive line and the connecting portion of the conductive line of the semiconductor device, in a case where the conductive line and the connecting portion of the conductive line are formed using Cu, as described above, there is a problem in that a copper oxide layer (CuO) (i.e., a natural oxide layer) forms on the copper layer.
Taking a closer look at the generating point of the copper oxide layer, the generating point can be generally classified into the following three sections. The first generating point of the copper oxide layer occurs when the contact hole (or via hole 105) and the trench 106 are formed to expose the upper surface of the first conductive line 103 by the selective patterning of the second insulating layer 104 deposited on the first conductive line. The second generating point occurs when the metal barrier 107 is deposited in the via hole 105 and the trench 106 and the copper seed layer for forming the copper bulk layer 108 is formed on the metal barrier 107 so that the natural oxide layer is formed on the copper seed layer. The third generating point occurs when the conductive layer (i.e., the copper bulk layer 108) fills the via hole 105 and the trench 106 and the copper bulk layer 108 is planarized with the second insulating layer by CMP process so that the copper oxide layer is formed on the second conductive line.
In such Dual Damascene process using copper as described above, the generation of copper oxide layer cannot be avoided. To remove the copper oxide layer in the prior art, the copper oxide layer is removed by plasma-processing using a mixture of H2 and Ar gas, or a mixture of H2 and He gas, or by heat treatment in H2 atmosphere.
The copper oxide layer formed on the copper seed layer causes a problem in that its formation thickness is so thin that the metal barrier 107 formed under the copper seed layer may be crystallized by the heat treatment at a high temperature, thus degrading the characteristics of the metal barrier.
The plasma treatment in the prior art also causes a thermal stress to be applied to the semiconductor substrate because the plasma treatment is performed at a temperature of above 300° C. Removing the copper oxide layer using heat-treatment under a hydrogen atmosphere is generally conducted at a temperature of about 150° C. This requires a fair amount of processing time to completely remove the copper oxide layer, thus causing the degradation of productivity of the semiconductor device.
U.S. Pat. No. 6,399,486, assigned to the Taiwan Semiconductor Manufacturing Company, discloses a method of resolving defects in the copper bulk layer that fills the via hole and the trench before performing CMP for the copper bulk layer. U.S. Pat. No. 6,399,486, however, does not disclose a solution for preventing or removing the various copper oxide layers described above.